library verilog;
use verilog.vl_types.all;
entity uart_top is
    port(
        sys_clk         : in     vl_logic;
        sys_rst_n       : in     vl_logic;
        uart_top_rx     : in     vl_logic;
        uart_data_out   : out    vl_logic_vector(7 downto 0);
        uart_rx_done    : out    vl_logic
    );
end uart_top;
